UofT VLSI Research Group - Access to restricted technology

CMC (the Canadian Microelectronics Corporation) provides information and technology design data for various integrated circuit fabrication technologies. This information is available under "/CMC/kits/" on VRG (VLSI Research Group), EECG research Group computer, Workstations Lab, and Energy Group research computer systems.

Available technologies include:
GF12LP - GlobalFoundries 12LP CMOS (via CMC)
GF22FDX-EXT - GlobalFoundries 22FDX-EXT CMOS SOI(via CMC)
GF45RF - GlobalFoundries 45nm RF CMOS SOI (via CMC)
GF45SPCLO - GlobalFoundries 45nm CMOS Photonics (via CMC)
CMOS65NM - STM 65-nanometre CMOS (via CMP)
TSMC65NM - TSMC 65-nanometre CMOS (via MOSIS)
TSMC90NM - TSMC 90-nanometre CMOS (via MOSIS)
TSMC130NM - TSMC 130-nanometre CMOS (via MOSIS)
CMRF8SF - IBM 0.13-micron CMOS (via MOSIS) and Artisan Libraries
AMSP35 - AMS 0.35-micron CMOS (basic and high-voltage) (via CMP)
AMISC5 - AMIS 0.5-micron CMOS (via MOSIS)
GA911 - Gennum bipolar array
CMOSP8 - Dalsa 0.8-micron CMOS (DK08G, DK08E, DK08C)

Older technologies; no more fabrication runs scheduled, but design data is still on-line
CMOSP18 - TSMC 0.18-micron CMOS (via PMC-Sierra and MOSIS) Note: This is being phased out in favour of CMRF8SF
CMOSP35 - TSMC 0.35-micron CMOS (via PMC-Sierra and MOSIS) Note: This is being phased out in favour of AMISC5
BICMOS - Nortel 0.8-micron BiCMOS (deprecated -- no more fab runs scheduled)
SIGE5HP - IBM 0.5-micron SiGe (deprecated -- no more fab runs scheduled)
SIGE5AM - IBM 0.5-micron SiGe (deprecated -- no more fab runs scheduled)
CMOS90NM - STM 90-nanometre CMOS (via CMP) (deprecated -- no more fab runs scheduled after July 2009 )

Licensing details and access vary, falling into several categories:

• Open to all university researchers, without additional non-disclosure agreements.
  These technologies include
  • ASCMOS, a fictitious 1-micron CMOS process used for teaching (no fabrication available)
  • SVCMOS, a fictitious 0.1-micron CMOS process used for teaching (no fabrication available)
  • BICMOS, a 0.8-micron BiCMOS process (no fabrication available)
  • GA911, a 2.5GHz bipolar device array with a 10-micron metal pitch (via Gennum)
  Some of these technologies are available for teaching only. Further runs may or may not be scheduled; check CMC's web-site http://www.cmc.ca for details.

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• Open to all university researchers upon signing a UofT "Confidential Information and Intellectual Property Agreement".
  This includes technologies for which the University has signed a Non-Disclosure Agreement with CMC and/or a fabrication facility, to provide access to local researchers without requiring them to sign an NDA with CMC. The University, though, requires that each person wishing to acquire access to the restricted information must first sign a "Confidential Information and Intellectual Property Agreement", available below. This second agreement states in part that you "have viewed a copy of the Technology Usage Agreement", so please read this before signing the CI/IP agreement.
  (Those who have already signed an individual CDA or NDA for these technologies need not sign this agreement.)
  After reading the CMC Technology Usage Agreement print the agreement for the selected technology:

  • CMOSP8:
    CI/IP for CMOSP8, a 0.8-micron CMOS process (Dalsa, via CMC)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.

  • CMOS65NM:
    CI/IP for CMOS65NM, a 65-nanometre CMOS process from ST Microelectronics, with fabrication via CMC and CMP (Circuits Multi-Projets, France)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.

  • CMOSP35:
    CI/IP for CMOSP35, a 0.35-micron CMOS process (TSMC via CMC and MOSIS)
    This document must be signed before a witness (usually the Course Lecturer or Supervisor), who must also sign the document.
    No more fab runs scheduled.

  • AMSP35:
    CI/IP for AMSP35, a 0.35-micron CMOS process (AMS via CMC and CMP)
    This document must be signed before a witness (usually the Course Lecturer or Supervisor), who must also sign the document.
    First fab run scheduled for 27 January 2010

  • CMOSP18:
    CI/IP for CMOSP18, a 0.18-micron CMOS process (TSMC via CMC and MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    No more fab runs scheduled.

    • Also useful for this technology:
      The Artisan Standard Cell Library for TSMC 0.18-micron CMOS
      This document must be co-signed by a Faculty Member who has also signed a copy of this document.

  • CMOS90NM:
    CI/IP for CMOS90NM, a 90-nanometre CMOS process from ST Microelectronics
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    No more fab runs scheduled.

  • GF45SPCLO, GF45RF, GF 22FDX-EXT and GF 12LP
    CI/IP covering GF technologies GF45RF, 22FDX-EXT and 12LP, 45nm SPCLO, 22nm CMOS SOI, and 12nm LP CMOS processes from GlobalFoundries
    This document must be co-signed by a Faculty Member who has also signed a copy of this document. (No co-signature required for faculty members.)
    For GF45SPCLO: you may be asked for a two- or three-slide presentation on your project when you submit a design for fabrication in this technology.

  Return the signed CI/IP agreement to

  Jaro Pristupa
  Pratt Building, Room 374C
  6 King's College Road
  email jaro.pristupa@utoronto.ca
  and access will be provided to you.

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• Open to all university researchers upon signing a UofT "Confidential Information and Intellectual Property Agreement" that includes the MOSIS "Individual NDA for University Students and Staff."
  This includes technologies for which our University's legal department has signed MOSIS's Non-Disclosure Agreement, for some technologies (notably, from IBM) where a company does not wish to allow CMC to re-distribute their design-kits. The University, though, requires that each person wishing to acquire access to the restricted information must first sign a "Confidential Information and Intellectual Property Agreement", and MOSIS requires that we report periodically the names of researchers who have been offered access.

  • TSMC65NM:
    CI/IP for TSMC's 65nm CMOS process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)

  • TSMC90NM:
    CI/IP for TSMC's 90nm CMOS process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)

    TSMC130NM:
    CI/IP for TSMC's 130nm CMOS process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)

  • CMRF8SF:
    CI/IP for CMRF8SF, IBM's 0.13-micron CMOS process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)

  • AMISC5:
    CI/IP for AMISC5, AMIS's 0.5-micron CMOS process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)

  • SIGE5HP/SIGE5AM:
    CI/IP for SIGE5HP and SIGE5AM, IBM's 0.5-micron Silicon Germainum (SiGe) process (via MOSIS)
    This document must be co-signed by a Faculty Member who has also signed a copy of this document.
    (Faculty Members must have their NDAs witnessed by another Faculty Member!)
    No more fab runs scheduled.

  
  Return signed CI/IP agreements to
  Jaro Pristupa
  Lab Manager, VLSI Research Group
  Pratt Building, Room 374C
  6 King's College Road
  
  and access will be provided to you.

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• Open to researchers who can provide a separate computer and disk storage, to be connected to a secure private network. The only external access is via direct link to the fabrication facility; there is no other way to transfer design data or simulation results to the regular research network.

  No technologies currently fall under this category.