VLSI Research Group - Publications: Conference Papers
1996
- M. Aliahmad and C.A.T. Salama,
"A 30V Line Driver in Submicron BiCMOS Technology",
International Symposium on Power Semiconductor Devices and IC's,"
Proceedings, pp. 61-64, 1996.
- V. Betz and J. Rose,
"Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,"
ICCAD 1996, pp. 652-659, Nov. 1996.
- J. Bismuth, A. Onthonos, M. Sweeny, A. Kevorkian and J.M. Xu,
"Superimposed Grating WDM on Ge-doped Silica-on-Silicon Planar Waveguide",
Conference on Lasers and Electro-Optics (CLEO/QELS), June 1996.
- S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley,
M. Gusat, K. Loveless, Z. Zilic, and S. Srbljic,
"Experience in Designing a Large-scale Multiprocessor using
Field-Programmable Devices and Advanced CAD Tools,"
33rd IEEE/ACM Design Automation Conference, Las Vegas, June 1996.
- J. Cai, J.K.O. Sin, V.M.C. Poon, W.T. Ng, and P.T. Lai,
"A fast Switching Insulated-gate p-i-n Diode Controlled Thyristor Structure,"
IEEE International Conference on Semiconductor Electronics,
pp. 122-125, 1996.
- V.C. Chan and D. Lewis,
"Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays",
Proc. Int. Symp. FPGAs 1996, pp 51-57, Feb. 1996.
- H. Chik, J. Bismuth and J.M. Xu,
"A 1x8 Supergrating Tap-off WDM Device",
CThB4, CLEO/Europe'96, Sept. 1996.
- P. Chow, S.O. Seo, J. Rose, K. Chung, and G. Paez,
"Architecture and Circuit-Level Design of an SRAM-Based Field-Programmable
Gate Array,"
IEEE Transactions on VLSI Systems, May 1996.
- K.I. Farkas, N.P. Jouppi, and P. Chow,
"Register File Design Configurations in Dynamically Scheduled Processors,"
2nd International Symposium on High-Performance Computer Architecture,
pp. 40-51, February 1996.
- B. Frey, F. Kschischang and P.G. Gulak,
"Early Detection and Trellis Splicing: Reducing Complexity of Soft
Iterative Decoding,"
Turbo Decoding Workshop, pp. 65-73, August 1996.
- B. Frey, F. Kschischang and P.G. Gulak,
"Speeding up Turbo-decoding by Trellis Splicing,"
Workshop on Turbo Codes, Lund, Sweden, August 1996.
- P.G. Gulak,
"Field Programmable Analog Arrays: A Status Report,"
Invited Paper, 4th Canadian Workshop on Field Programmable Devices (FPD'96),
Toronto, May 1996.
- P.G. Gulak and D. D'Mello,
"Field Programmable Analog Arrays: Review and Future Perspectives,"
SPIE Conference, October 1996.
- F. Hansen and C.A.T. Salama,
"Clock and Data Recovery IC and Demultiplexer for 2.5 Gb/s ATM Physical
Layer Controller",
ISCAS, Proceedings, pp. 125-129, 1996.
- X. Hu and K. Martin,
"A Switched-Current Sample-and-Hold Circuit,"
1996 International Symposium on Circuits and Systems,
pp. 191-194, May 1996.
- M. Hutton, J.P. Grossman, J. Rose, D. Corneil,
"Characterization and Parameterized Random Generation of Digital Circuits,"
IEEE/ACM Design Automation Conference, pp. 94-99, June 1996.
- S. Jantzi, K. Martin, A. Sedra,
"The Effects of Mismatch in Complex Bandpass D-A Modulators,"
1996 International Symposium on Circuits and Systems,
pp. 227-231, May 1996.
- D.A. Johns and D. Essig,
"Integrated circuits for data transmission over twisted-pair channels,"
Invited Paper, IEEE Custom Integrated Circuits Conference, pp. 5-12, May 1996.
- A. Kaviani and S. Brown,
"Hybrid FPGA Architecture,"
International Symposium on Field-Programmable Gate Arrays (FPGA '96),
Monterey, CA, Feb. 1996, pp. 1-7.
- D. Lewis,
"Interleaved IIR Filter on Delta-Sigma Modulated Signals",
Conference on Advanced Signal Processing Algorithms, Architectures, and
Implementation, Proceedings, pp. 55-62, Aug. 1996
- M. Liu, C.A.T. Salama, P. Schvan and M. King,
"A Fully Resurfed BiCMOS Compatible High Voltage MOS Transistor,"
International Symposium on Power Semiconductor Devices and IC's,
Proceedings, pp. 143-147, 1996.
- J.R. Long, M.A. Copeland, S. Kovacic, D.S. Malhi and D.L. Harame,
"RF Analog and Digital Circuits in SiGe Technology,"
International Solid-State Circuits Conference, Proceedings,
pp. 82-82, Feb. 1996.
- J.R. Long, M.A. Copeland,
"Modeling, Characterization and Design of Monolithic Inductors for
Silicon RFICs",
IEEE Custom Integrated Circuits Conference, pp. 185-188, May 1996.
- J. Omidi, P.G. Gulak and S. Pasupathy,
"Parallel Structures for Joint Channel Estimation and Data Detection over
Fading Channels,"
1996 Workshop on VLSI Signal Processing, Proceedings, pp. 325-326,
October 1996.
- J. Omidi, S. Pasupathy, and P.G. Gulak,
"Joint Data and Kalman Estimation of Fading Channels using a Generalized
Viterbi Algorithm,"
1996 IEEE International Communications Conference (ICC), Proceedings,
vol 2, pp. 1198-1203, June 1996.
- S. Rezania and K. Martin,
"Power Design: A Module Generator for General-Purpose Amplifiers,"
1996 International Symposium on Circuits and Systems,
pp. 215-219, May 1996.
- M.A.R. Saghir, P. Chow, and C. Lee,
"Exploiting Dual Memory Banks in Digital Signal Processors,"
1996 SIGARCH Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS VII), pp. 234-243, Boston, MA,
October 1996.
- E.H. Sargent, D. Pavlidis, R. Clayton, H. Kim, and J.M. Xu,
"Profiling of Carrier Density in Semiconductor Lasers via Spectra Analysis
of Side Spontaneous Emission",
CLEO/Europe'96, Sept. 1996.
- E.H. Sargent, G.L. Tan, D.A. Suda and J.M. Xu,
"Internal Operating Mechanisms of OEIC-compatible Lateral Injection Lasers:
Intrinsic Differences from the Vertical Injection Paradigm",
15th International Semiconductor Laser Conference, Oct. 1996.
- E.H. Sargent and J.M Xu,
"Investigations of Lateral Current Injection Lasers: Internal Operating
Mechanisms and Doping Profile Engineering",
23 International Symposium on Compound Semiconductors, Sept. 1996.
- A. Sheikholeslami, P.G. Gulak, and T. Hanyu,
"A Multiple-Valued Ferroelectric Content-Addressable Memory,"
International Symposium on Multiple-Valued Logic, Proceedings, pp. 74-79, 1996.
- T. Sowlati, Y. Greshishchev, C.A.T. Salama, G. Rabjohn and J. Sitch,
"Linearized High Efficiency Class Power Amplifier for Wireless Communications",
Custom Integrated Circuits Conference, Proceedings, pp. 201-204, 1996
- S. Wilton, J. Rose, Z. Vranesic,
"Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory
Arrays,"
IEEE CICC, pp. 144-147, May 1996.
- R.D. Wittig and P. Chow,
"OneChip: An FPGA Processor With Reconfigurable Logic,"
The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines
FCCM'96,
March 1996.
- D. Yeh, G. Feygin, and P. Chow,
"RACER: A Reconfigurable Constraint-Length 14 Viterbi Decoder,"
The Fourth Annual IEEE Symposium on FPGAs for Custom Computing
Machines FCCM'96, March 1996.
- Z. Zilic and Z.G. Vranesic,
"New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms,"
26th IEEE International Symposium on Multiple-valued Logic, May 1996.
- Z. Zilic and Z.G. Vranesic,
"Using BDDs to Design ULMs for FPGAs,"
Proceedings, FPGA '96 - International Symposium on Field Programmable
Gate Arrays, pp. 24-30, Feb. 1996.
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