VLSI Research Group - Publications: Conference Papers
1997
- J. Ahmed and S. Zaky,
"Asynchronous Design in Dynamic CMOS,"
Canadian Conference on Electrical and Computer Engineering, Proceedings, pp.
528-531, May 1997.
- M. Aliahmad and C.A.T. Salama,
"A Short Loop SLIC in a Submicron BiCMOS Technology",
IEEE/IEEJ International Symposium on Power Semiconductor
Devices, Proceedings, pp. 329-332, 1997.
- J. Anderson and S. Brown, "An LPGA with Foldable PLA-Style Logic Blocks,"
International Symposium on FPGAs, Monterey Bay, CA, February 1997.
- V. Betz and J. Rose,
"Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing
and Size,"
IEEE CICC 1997.
- V. Betz and J. Rose,
"VPR: A New Packing, Placement and Routing Tool for FPGA Research,"
7th International Workshop on Field-Programmable
Logic, pp. 213-222, August 1997.
- V.C. Chan and D. Lewis,
"Hierarchical Partitioning for Field-Programmable Systems,"
IEEE International Conference on Computer-Aided Design, Proceedings, pp.
428-435, November 1997.
- K. Farkas, P. Chow, N. Jouppi, and Z. Vranesic,
"Memory-System Design Considerations for Dynamically-Scheduled
Processors,"
24th Annual International Symposium on Computer Architecture,
Proceedings, pp. 133-143, June 1997.
- K. Farkas, P. Chow, N. Jouppi, and Z. Vranesic,
"The Multicluster Architecture: Reducing Cycle Time Through
Partitioning,"
30th Annual International Symposium on Microarchitecture: MICRO-30,
Proceedings, pp. 149-159, December 1997.
- B. Frey, F. Kschischang, and P.G. Gulak,
"Concurrent Turbo-Decoding,"
ISIT, Ulm, Germany, June 1997.
- N. Fujishima and C.A.T. Salama,
"A Trench Lateral Power MOSFET using Self Aligned Trench Bottom Contacts",
IEDM, Proceedings, pp. 359-362, 1997.
- V. Gaudet and P.G. Gulak,
"CMOS Implementation of a Current Conveyor-Based Field Programmable Analog
Array,"
31st Asilomar Conference, Signals, and Computers, November 1997.
- F. Hansen and C.A.T. Salama,
"2.5Gb/s ATM Physical Layer Controller in 0.8um BiCMOS",
European Solid State Circuits Conference, Proceedings, pp. 96-99, 1997.
- M. Hutton, J. Rose, D. Corneil,
"Generation of Synthetic Sequential Benchmark Circuits,"
FPGA '97, ACM Symposium on FPGAs, Feb. 1997.
- S. Jantzi, K. Martin, and A. Sedra,
"A Quadrature Bandpass Modulator for Digital Radio,"
IEEE International Symposium on Solid-State Circuits Digest of Technical
Papers, pp. 216-217, February 1997.
- M. Khalid and J. Rose,
"Experimental Evaluation of Mesh and Partial Crossbar
Routing Architectures for Multi-FPGA Systems,"
IFIP IWLAS '97,
International Workshop on Logic and Architecture Synthesis,
pp. 119-127, December 1997.
- G.G.F. Lemieux, S.D. Brown, D. Vranesic, "On Two-Step Routing for FPGAs,"
ISPD, Napa Valley, CA, pp 60-66, April 1997.
- D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow,
"The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System,"
FPGA '97, ACM Symposium on FPGAs, Feb. 1997.
- K. Martin,
"Small Side-Lobe Filter Design for Multi-Tone Data Communication
Applications,"
European Conference on Signal Processing, September 1997.
- J. Omidi, P.G. Gulak, and S. Pasupathy,
"Joint Data and Channel Estimation Using the Per-Branch Processing Method,"
IEEE Signal Processing Workshop on Wireless Communications, Proceedings, pp.
389-392, April 1997.
- J. Ranaweera, A. Dibu-Caiole, W.T. Ng and C.A.T. Salama,
"ONO Interpoly Dielectrics for Novel Flash E2PROM Cells",
Canadian Semiconductor Technology Conference, Proceedings, pp. 42, 1997.
- J. Ranaweera, I. Kalastirsky, A. Dibu-Caiole, W.T. Ng and C.A.T. Salama,
"Performance Limitations of a Flash E2PROM Cell, Programmed with Zener
Induced Hot Electrons,"
Non Volatile Semiconductor Memory Symposium, Proceedings, paper 2.2, 1997.
- J. Rose and D. Hill,
"Architectural and Physical Design Challenges for One-Million Gate FPGAs
and Beyond,"
FPGA '97, ACM Symposium on FPGAs, February 1997.
- K. Schultz and P.G. Gulak,
"Throttled-Buffer ATM Switch Output Control Circuitry with CAM-Based Multicast
Support,"
ISSCC, Proceedings, pp. 152-153, February 1997.
- A. Sheikholeslami and P.G. Gulak,
"Multivalued Ferroelectric Associative Memory Design,"
6th Workshop on Post-Binary ULSI Systems, pp. 68-69, May 1997.
- Z.G. Vranesic,
"Ring-Based Multiprocessors: The NUMAchine and Hector Experience,"
Workshop on New Technologies, Interconnects and Communications in
Distributed and Parallel Systems, June 1997.
- Q. Wang and D. Lewis,
"Automated Field-Programmable Compute Accelerator Design Using Partial
Evaluation,"
IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings, pp.
176-185, 1997.
- S. Wilton, J. Rose, Z. Vranesic,
"Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays,"
FPGA '97, ACM Symposium on FPGAs, Feb. 1997.
- Z. Zilic, Z.G. Vranesic and K. Radecka,
"A Deterministic Multivariate Interpolation Algorithm for Small Finite
Fields,"
Waterloo, Ontario, August 1997.
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