VLSI Research Group - Publications: Conference Papers

• T. Aamodt and P. Chow, "Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000), pp. 128-137, November 2000.
• P. Aarabi and S.G. Zaky, "Iterative Spatial Probability Based Sound Localization," 4th World Multiconference on Circuits, Systems, Communications and Computers (CSCC 2000), Athens, July 2000.
• P. Aarabi and S.G. Zaky, "Integrated Vision and Sound Localization," International Conference on Information Fusion, Paris, July 2000.
• E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," International Symposium on FPGAs, pp. 3-12, February 2000.
• V. Betz and J. Rose, "Automated Generation of International Symposium on FPGAs Architectures," International Symposium on FPGAs, pp. 175-186, February 2000.
• S. Bodapati and F.N. Najm, "Pre-layout Estimation of Individual Wire Lengths," ACM International Workshop on System-Level Interconnect Prediction, San Diego, CA, pp. 93-98, April 2000.
• K.M. Buyuksahin and F.N. Najm, "High-level Power Estimation with Interconnect Effects," IEEE International Symposium on Low Power Electronics and Design, Italy, pp. 197-202, July 2000.
• H. Djahanshahi and C.A.T. Salama, "A Two Stage Differential CCO Implementation in Submicron CMOS," Midwest Symposium on Circuits and Systems, Lansing, August 2000.
• T. Esmailian, G. Gulak and F. Kschischang, "A Discrete Multitone Power Line Communications System, International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2000), Istanbul, Turkey.
• T. Esmailian, F. Kschischang and G. Gulak, "Simulation of a Discrete Multitone System Over In-Building Power Line," 20th Biennial Symposium on Communications, Queen's University, Kingston, Canada, May 2000.
• T. Esmailian, F. Kschischang and G. Gulak, "Characteristics of In-Building Power Lines at High Frequencies and their Channel Capacity," International Symposium on Power-Line Communications and its Applications, pp. 52-59, Limerick, Ireland, 2000.
• R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic, "The NUMAchine Multiprocessor," IEEE/IACC International Conference on Parallel Processing, Toronto, Ontario, pp. 487-496, 2000.
• A. Hadji-Abdolhamid and D.A. Johns, "ADC Resolution Enhancement by an Analog Decorrelator," IEEE International Symposium on Circuits and Systems, Geneva, June 2000.
• H. Jin and C.A.T. Salama, "A 1V, 1.9GHz CDMA, CMOS on SOI, Low Noise Amplifier," IEEE International SOI Conference, Wakefield, pp. 102-103, 2000.
• A. Kaviani and S. Brown, "Technology Mapping Issues for an International Symposium on FPGAs with Lookup Tables and PLA-like Blocks," International Symposium on FPGAs, Monterey, CA, pp. 60-66, February 2000.
• A. Khoueir, Z.H. Lu, W.T. Ng, S.P. Tay, "Growth of Ultrathin Nitride on Si (100) by Rapid Thermal N2 Treatment," Electrochemical Society Conference on Rapid Thermal and other Short-time Processing Technology, pp. 223-226, Toronto, Ontario, May 2000.
• G. Lemieux, P. Leventis and D. Lewis, "Generating Highly-Routable Sparse Crossbars for PLDs," International Symposium on FPGAs, February 2000.
• R. Mahadevan and D.A. Johns, "A Differential 160MHz Self-terminating Adaptive CMOS Line Driver," IEEE International Symposium on Solid-State Circuits, San Francisco, CA, pp. 436-437, February 2000.
• J.P. Maligeorgos and J.R. Long, "A 2V 5.1-5.8GHz Image-Reject Receiver with Wide Dynamic Range," IEEE International Symposium on Solid-State Circuits, San Francisco, CA, pp. 322-323, February 2000.
• A. Marquardt, V. Betz and J. Rose, "Timing-Driven Placement for FPGAs," International Symposium on FPGAs, pp. 203-213, February 2000.
• K. Martin, "Hierarchical Quadrature Amplitude Modulation," Invited Opening Keynote Address, IEEE NORCHIP Conference, Turku, Finland, November 2000.
• S. Mirabbasi, S. Gazor, and K. Martin, "A Wideband Carrier-Recovery System for Multilevel QAM Signals," IEEE International Symposium on Circuits and Systems 2000, pp. 661-664, Geneva, Switzerland.
• S. Nassif, S. Honarkhah and C.A.T. Salama, "Low Voltage CMOS Compatible Power MOSFET for On-chip DC-DC Converters," IEEE/IEEJ International Symposium on Power Semiconductor Devices, Toulouse, pp. 43-46, 2000. (Winner of the Best Paper Award.)
• A. Sheikholeslami and P.G. Gulak, "A Survey of Reference Generation Techniques for Ferroelectric Memories," 12th International Symposium on Integrated Ferroelectrics, Aachen, Germany, March 2000.
• D. Suvakovic and C.A.T. Salama, "A Pipelined Multiply Accumulate Unit Design for Energy Recovery DSP Systems," IEEE International Symposium on Circuits and Systems, Geneva, Proceedings, vol. 1, pp. 16-19, 2000.
• D. Suvakovic and C.A.T. Salama, Two Phase Non-Overlapping Clock Adiabatic Differential Cascode Voltage Switch Logic," IEEE International Symposium on Solid-State Circuits, San Francisco, Technical Digest, pp. 364-365, 2000.
• D.H.S. Tam and W.T. Ng, "A Novel Mixed-Mode Adaptive Equalization System for High-Speed 2-Level PAM Signals," IEEE International Symposium on Circuits and Systems, paper no. IV-749, Geneva, Switzerland, June 2000.
• W. An and C.A.T. Salama, "An 8-bit 1 Gsample/s Folding Interpolated Analog to Digital Converter," European Solid State Circuits Conference (ESSCIRC), Stockholm, pp. 200-204, 2000.
• G. Yoh and F.N. Najm, "A Statistical Model for Electromigration Failure," 1st International Symposium on Quality Electronic Design, San Jose, CA, pp. 45-50, March 2000.
• S. Ye and C.A.T. Salama, "A 1V, 1.9GHz, Low Distortion Dual Gate CMOS on SOI Mixer," IEEE International SOI Conference, Wakefield, pp. 102-103, 2000.
• L. Zhang, Q. Wang and D. Lewis, "Design of a VLIW Compute Accelerator on the Transmogrifier-2," IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000.

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