VLSI Research Group - Publications: Full Journal Papers
1998
- M. Aliahmad and C.A.T. Salama,
"A High Voltage Line Driver for Subscriber Loop Interfaces in a Low Voltage
Submicron BiCMOS Process,"
Journal on Analog Integrated Circuits and Signal Processing, vol. 15, pp.
261-274, 1998.
- M. Aliahmad and C.A.T. Salama,
"Integration of a Short Loop SLIC in a Low Voltage Submicron BiCMOS
Technology,"
IEEE Journal of Solid-State Circuits, vol. 33, pp. 750-7585, 1998.
- V. Betz and J. Rose,
"Effect of the Prefabricated Routing Track Distribution on FPGA
Area-Efficiency,"
IEEE Transactions on VLSI, vol. 6, no. 3, pp. 445-456, September 1998.
- V. Betz and J. Rose,
"How Much Logic Should Go in an FPGA Logic Block?",
IEEE Design & Test Magazine, vol. 15, no. 1, pp. 10-15, Jan-March 1998.
- X.B. Chen, P.A. Mawby, K. Board, and C.A.T. Salama,
"Theory of a Novel Voltage Sustaining Layer for Power Devices,"
Microelectronics Journal, vol. 29, pp. 1005-1011, 1998.
- D. D'Mello and P.G. Gulak,
"Design Approaches to Field-Programmable Analog Integrated Circuits,"
Analog Integrated Circuits and Signal Processing, Special Issue on
Programmable Analog Systems, Kluwer Academic Publishers, vol. 17, no.
1-2, pp. 7-34, September 1998.
- D. Gajski, J. Zhu and R. Doemer,
"Specification and Design of Embedded Systems,"
it+ti, Oldenbourg Verlag, GmbH, Munich, Germany, March, 1998.
- W. Gross and P.G. Gulak,
"Simplified MAP Algorithm Suitable for Implementation of Turbo Decoders,"
Electronics Letters, vol. 34, no. 16, pp. 1577-1578, August 1998.
- D. Hiemstra, A. Kizeev, L. Hou and C.A.T. Salama,
"Low Frequency Performance of GaAs MESFET Devices Under Gamma Irradiation
Conditions,"
IEEE Transactions on Nuclear Science, vol. 45, pp. 2616-2623, 1998.
- D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow,
"The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System,"
IEEE Transactions on VLSI Systems, 6(2):188-198, June 1998.
- K.W. Li, S. Zaky and K.G. Balmain,
"Effect of RFI on the Error Probabilities of Synchronizer Circuits,"
IEEE Transactions on Circuits and Systems, Part I, pp. 1052-1061, October
1998.
- K. Lowe and P.G. Gulak,
"A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay
and Power in CMOS and BiCMOS Combinational Logic,"
IEEE Transactions on CAD, vol. 17, no. 5, pp. 419-434, May 1998.
- K. Martin,
"Small Side-Lobe Filter Design for Multi-Tone Data Communication
Applications,"
IEEE Transactions on Circuits and Systems, vol. 45, no. 8, pp. 1155-1161,
August 1998.
- F. N. Najm and M. G. Xakellis,
"Statistical estimation of the switching activity in VLSI circuits,"
VLSI Design, vol. 7, no. 3, pp. 243-254, 1998.
- J. Omidi, P.G. Gulak, and S. Pasupathy,
"Parallel Structures for Joint Channel Estimation and Data Detection
Over Fading Channels,"
IEEE Transactions on Selected Areas of Communications (special issue
on Signal Processing and Wireless Communications), vol. 16, no. 9, pp.
1616-1629, December 1998.
- R. Panda and F. N. Najm,
"Post-mapping transformations for low-power synthesis,"
VLSI Design, vol. 7, no. 3, 1998.
- M. Shakiba, D. Johns, K. Martin,
"An Integrated 200MHz 3.3V BiCMOS Class-IV Partial-Response Analog
Viterbi Decoder,"
IEEE Journal of Solid State Circuits, vol. 33, pp. 61-75, January
1998.
- M. Shakiba, D. Johns, K. Martin,
"BiCMOS Circuits for Analog Viterbi Decoders,"
IEEE Transactions on Circuits and Systems - II: Analog and Digital
Signal Processing, vol. 45, pp. 1527-1537, December 1998. [This paper
won the IEEE Darlington Best Paper Award for IEE Trans. on Circuits
and Systems.]
- Z. Zilic and Z.G. Vranesic,
"Using Decision Diagrams to Design ULMs for FPGAs,"
IEEE Transactions on Computers, vol. 47, no. 9, pp. 971-982, 1998.
Return to
UofT VRG home page
Comments to webmaster@vrg.utoronto.ca
http://www.vrg.utoronto.ca/vrg/publications/FJP.1998.html
-- Last updated: December 2000