VLSI Research Group - Publications: Full Journal Papers
- E. Boutillon, W. Gross, G. Gulak,
"Gestion de la Memoire pour L'Algorithme du Forward Backward,"
5eme Workshop AAA sur 'Adequation Algorithme Architecture, INRIA
Rocquencourt, France, January 2000.
- A. Carusone and D.A. Johns, "Analogue Adaptive Filters: Past and Present,"
IEE Proceedings - Circuits, Devices an Systems, pp. 82-90, February 2000.
- H. Djahanshahi and C.A.T. Salama, "Differential CMOS Circuits for
622MHz/933MHz Clock and Data Recovery Applications, IEEE Journal of
Solid-State Circuits, vol. 35, pp. 847-855, 2000.
- V. Gaudet and G. Gulak, "Implementation Issues for High-Bandwidth
Field-Programmable Analog Arrays,"
Journal of Circuits, Systems and Computers Special Issue on Analog and
Digital Arrays, World Scientific Publishing, 2000.
- S. Gupta and F.N. Najm, "Analytical Models for RTL Power Estimation of
Combinational and Sequential Circuits," IEEE Transactions on Computer-Aided
Design, vol. 19, no. 7, pp. 808-814, July 2000.
- S. Gupta and F.N. Najm, "Power Modeling for High Level Power Estimation,"
IEEE Transactions on VLSI, vol. 8, no. 1, pp. 18-29, February 2000.
- M. Khalid and J. Rose, "A Novel and Efficient Routing Architecture for
Multi-FPGA Systems, IEEE Transactions on VLSI,
vol. 8, no. 1, pp. 30-39, February 2000.
- A. Khoueir, Z.H. Lu, W.T. Ng and Y. Ma, "Ultrathin Oxynitride Formation by
Low Energy Ion-Implantation," Journal of Vacuum Science Technology, vol. 18,
no. 2, pp. 724-729, March 2000.
- J.R. Long, "A 5.1-5.8GHz Low-Power Image-Reject Downconverter," IEEE Journal
of Solid-State Circuits, vol. 35, no. 9, pp. 1320-1328, September 2000.
- J.R. Long, "Monolithic Transformers for Silicon RF IC Design," IEEE Journal
of Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, September 2000.
- J.P. Maligeorgos and J.R. Long, "A 2V 5.1-5.8GHz Image-Reject Receiver with
Wide Dynamic Range," IEEE Journal of Solid-State Circuits, December 2000.
- A. Marquardt, V. Betz and J. Rose, "Speed and Area Trade-offs in
Cluster-Based FPGA Architectures, IEEE
Transactions on VLSI, vol. 8, no. 1, pp. 84-93, February 2000.
- S. Mirabbasi and K. Martin,
"Classical and Modern Receiver Architectures,"
IEEE Communications Magazine, pp. 132-139, Nov. 2000.
- S. Mirabbasi and K. Martin,
"Hierarchical QAM: A Spectrally-Efficient DC-Free Modula-tion Scheme,"
IEEE Communications Magazine, pp. 140-146, Nov. 2000.
- M. Ramezani and C.A.T. Salama, "A 0.8um BiCMOS Gate Driver for IGBT Power
Switch," Journal of Analog Integrated Circuits and Signal Processing, vol.
24, pp. 175-185, 2000.
- J. Ren and C.A.T. Salama,
"A 1V SOI NMOSFET with Suppressed Floating Body Effects,"
Solid State Electronics, vol. 44, pp. 1931-1937, 2000.
- A. Sheikholeslami, P.G. Gulak, H. Takauchi, H. Tamura, H. Yoshioka and T.
Tamura, "A pulse-based, parallel-element macromodel for ferroelectric
capacitors," IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency
Control," vol. 47, no. 4, pp. 784-791, July 2000.
- A. Sheikholeslami and P.G. Gulak, "A Survey of Circuit Innovations in
Ferroelectric Random-Access Memories," Proceedings of the IEEE, vol. 88, no.
3, pp. 667-689, May 2000.
- D. Suvakovic and C.A.T. Salama, "A Low Vt CMOS Implementation of a LPLV
Digital Filter Core for Portable Audio Applications," IEEE Transactions on
Circuits and Systems II, vol. 47, pp. 1297-1300, 2000.
- L.L. Zhang, B. Beacham, M.R. Hashemi, P. Chow, and A. Leon-Garcia, "A
Scheduler ASIC for a Programmable Packet Switch," IEEE Micro, 20(1):42-48,
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-- Last updated: December 2000