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RF base station applications |
Narrow base-width
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Exceed the Johnson Limit that governs high frequency and high breakdown voltage operation |
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1. Reduce gate
to drain overlap capacitance
2. Reduce gate drive loss
3. More efficient power converters
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4. Reduce gate to drain overlap capacitance
5. Reduce gate drive loss
6. More efficient power converters
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World’s first high voltage version of the FINFET
- FINFET will be one of the next generation transistor after conventional CMOS technology reaches its final scaling limit (e.g. <20nm)
- Prototypes were fabricated using a 0.5µm CMOS compatible technology
- First experimental demonstration of the power FINFET concept.
- Readying for the integration of power devices into future VLSI technologies
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Novel utilization of field plate technique to provide significant improvement in breakdown voltage
- Improvement is by layout changes only. No added cost or processing changes (i.e. free!)
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First demonstration of a power management system using DVS and custom designed integrated DC-DC converter.
- World’s first demonstration of a reconfigurable DC-DC converter!
- Significant improvement in conversion efficiency for light load with no added complexity or cost.
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World’s first demonstration of suppressing EMI using digital spread spectrum technique (patented)
- A pseudo random number generator is used to vary the switching frequency.
- This technology was sold to On Semiconductor in 2009
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A distortion suppression technique for all digital class D audio amplifier using local feedback
- The amplifier is implemented using a 0.35µm 40V CMOS technology
- The amplifier is implemented using a 0.35µm 40V CMOS technology
- Excellent distortion performance, enabling this amplifier to compete in the high fidelity market
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A novel dead-time correction method to continuously adjust the dead-time to eliminate unwanted body-diode conduction to improve efficiency
- Automated optimization even with varying load
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Using a dual output stage, a large inductor is used for steady state, and a smaller inductor is used for load transient
- A digital controller will trigger a sequence of linear and non-linear compensation algorithm to quickly suppress any output variations due to sudden load changes.
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- World’s first demonstration of a digital thermal management system to equalize the temperature of each converter to improve reliability
- Peak temperature is reduced
- Average temperature is similar across all converters
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A gate driving technique using dynamically programmable output resistance to optimize switching speed and EMI.
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A gate driving technique using dynamically programmable output resistance to optimize current balancing between IGBTs
- A custom gate driver IC is implemented using TSMC’s 0.18mm BCD Gen-II High Voltage process
- Chip area: 750mm x 520mm
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This Class-D H-bridge Amplifier IC is designed by Jingshu Yu, Ge Jin and Robert Mckenzie. This is initiated with a simple idea: Output stage ringing is significantly influenced by the output resistance of gate drivers. Hence, they built up a binary weighted segmented gate driver to adjust the gate drivers size on the fly. By controlling the gate driver size, the output resistance is lowered during steady state and increased during the transition time.
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This is a LDMOS output stage IC designed by Junmin Lee and tested by Simon Jin.
The objective of this research is to design and optimize power MOSFET output stages for high-frequency integrated DC-DC converters. This includes the development and demonstration of metal layout optimization techniques for large lateral power MOSFETs, and an optimized output stage design methodology to maximize the efficiency of DC-DC converters. With a segmented output stage, enabling and disabling each segment changes the effective width of the power transistors.
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