University of Toronto | The Edward S.Rogers Sr.Department of Electrical & Computer Engineering

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Refereed journal publications (published or accepted)
  1. J. Wang, A. Prodić, W.T. Ng, “Mixed-Signal-Controlled Flyback-Transformer-Based Buck Converter with Improved Dynamic Performance and Transient Energy Recycling,” IEEE Trans. Power Electronics, Vol. 28, No. 2, pp. 970-984, 2013.
  2. G. Xie, E. Xu, J. Lee, N. Hashemi, B. Zhang, F.Y. Fu and W.T. Ng, “Breakdown Voltage Enhancement Technique for RF Based AlGaN/GaN HEMTs with a Source-connected Air-bridge Field Plate,” IEEE Electron Device Lett. Vol. 33, No. 5, pp. 670-672, 2012.
  3.   G. Xie (谢刚), E. Xu, N. Hashemi, B. Zhang (张波), F.Y. Fu and W.T. Ng, “An AlGaN/GaN HEMT with Reduced Surface Electric Field and Improved Breakdown Voltage,” Chinese Physics B, Vol. 21, No. 8 (2012) 086105, 2012.
  4. G. Xie, E. Xu, B. Zhang, W.T. Ng, “Study on Breakdown Failure Mechanism of Power AlGaNGaN HEMTs on a RF Compatible Process,” Microelectronics Reliability, Vol. 52, No. 6, pp. 964-968, June 2012.
  5. W.M. Tang, M.G. Helander, M.T. Greiner, Z.H. Lu and W.T. Ng, “Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric,” Active and Passive Electronic Components, Volume 2012 (2012), Article ID 901076, 5 pages.
  6. W.M. Tang, M.T. Greiner, Z.H. Lu, W.T. Ng and H.G. Nam, “Effects of UV-ozone treatment on radio-frequency magnetron sputtered ZnO thin films,” Thin Solid Films, Vol. 520, pp. 569-573, July 2011.
  7. W. M. Tang, M. T. Greiner, M. G. Helander, Z. H. Lu, and W.T. Ng, “Effects of interfacial oxide layers of the electrode metals on the electrical characteristics of organic thin-film transistors with HfO2 gate dielectric,” J. of Applied Physics, Vol. 110, No. 4, 044108 (2011).
  8. O. Trescases, A. Prodić, and W.T. Ng, “Digitally Controlled Current-Mode DC-DC Converter IC,” IEEE Trans. Circuits and Systems I, Vol. 58, No. 1, pp. 219 – 231, 2011.
  9. W. M. Tang, W. T. Ng, M. G. Helander, M. T. Greiner, Z. H. Lu, “UV ozone passivation of the metal/dielectric interface for HfO2-based organic thin film transistors,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 28, No. 6, pp. 1100 – 1103, 2010.
  10. A. Yoo, Y. Onishi, H.P.E. Xu, W.T. Ng, “A Low-Voltage Lateral SJ-FINFET With Deep-Trench p-Drift Region,” IEEE Electron Device Lett., Vol. 30, No. 8, pp. 858-860, Aug. 2009.
  11. H. Wang, H.P.E. Xu, W.T. Ng, “A Novel Orthogonal Gate EDMOS Transistor With Improved dv/dt Capability and Figure of Merit (FOM),” IEEE Electron Device Lett., Vol. 29, No. 12, pp. 1386-1388, Dec. 2008.
  12. H. Wang, H.P.E. Xu, W.T. Ng, “Observation and Utilization of Boron Segregation in Trench MOSFETs to improve Figure-of-Merit (FOM),” IEEE Electron Device Lett., Vol. 29, No. 11, pp. 1239-1241, Nov. 2008.
  13. O. Trescases, G. Wei, A. Prodic, and W.T. Ng, “Predictive Efficiency Optimization for DC-DC Converters with Digital Electronic Loads,” IEEE Trans. Power Electronics, IEEE Trans. Power Electronics, Vol. 23, No. 4, pp. 1859-1869, July 2008.
  14. G. Yip, J. Qiu, W.T. Ng, and Z.H. Lu, “Effect Of Metal Contacts On The Electrical Characteristics Of Al2O3 Dielectric Thin Films,” Appl. Phys. Lett. 92, 122911, Mar. 2008.
  15. R. Azar, F. Udrea, W.T. Ng, F. Dawson, W. Findlay, and P. Waind, “The Current Sharing Optimization of Paralleled IGBTs in a Power Module Tile Using a PSpice Frequency Dependent Impedance Model,” IEEE Trans. Power Electronics, Vol. 23, No. 1, pp. 206-217, Jan. 2008.
  16. H.P.E. Xu, O.P. Trescases, I-S.M. Sun, D. Lee, W.T. Ng, K. Fukumoto, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, S. Tamura, K. Takasuka, and T. Kohno, “Design of a Rugged 60V VDMOS Transistor,” Circuits, Devices & Systems, IET, Vol. 1, No. 5, pp. 327-331, October 2007.
  17. O. Trescases, G. Wei, A. Prodic, W.T. Ng, “An EMI Reduction Technique for Digitally Controlled SMPS,” IEEE Trans. Power Electronics, Vol. 22, No. 4, pp. 1560-1565, July 2007.
  18.    I-S. M. Sun, W. T. Ng, .K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, H. Imai, A. Ishikawa, S. Tamura, and K. Takasuka, “Lateral High-Speed Bipolar Transistor on SOI for RF SoC Applications,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1376-1383, July 2005.
  19. R. Azar, F. Udrea, W.T. Ng, F. Dawson, W. Findlay, P. Waind, and G. Amaratunga, “The Current Sharing Optimisation of Paralleled IGBTs in a Power Module Tile Using a PSpice Frequency Dependent Impedance Model,” IEEE Trans. Industry Applications, Vol. 40, No. 3, pp. 710-716, May/June 2004. (with Dynex Semiconductor, UK)
  20. R. Azar, F. Udrea, W.T. Ng, F. Dawson, W. Findlay, P. Waind and G. Amaratunga, “Advanced Electrothermal Spice Modelling Of Large Power IGBTs,” IEE Proc.-Circuits Devices Syst., Vol. 151, No. 3, pp. 249-253, June 2004. (with Dynex Semiconductor, UK)
  21. M. Lee, Z.H. Lu, W.T. Ng, D. Landheer, X. Wu, and S. Moisa, “Interfacial Growth in HfOxNy Gate Dielectrics Deposited Using [(C2H5)2N]4Hf with O2 and NO,” Applied Physics Letters, Vol. 83, No. 13, pp. 2638-2640, Sep. 2003.

Refereed conference publications (published or accepted)

  1. W.M. Tang, M.G. Helander, M.T. Greiner, J. Qiu, Z.H. Lu, and W.T. Ng, “A Study on the Electrical Characteristics of Copper Phthalocyanine-based OTFTs with ZrTaO as Gate Dielectric,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Jun. 3-5, 2013. (Accepted for publication)
  2. Z. Ning, L. He, Z. Hu, G. Jin and W.T. Ng, “A Feedback-Voltage-Sensing Translator for Floating Buck DC-DC Converters,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Jun. 3-5, 2013. (Accepted for publication)
  3. M. Sasaki, H. Nishio, A. Shorten and W.T. Ng, “Current Balancing Control for Parallel Connected IGBTs Using Programmable Gate Driver Output Resistance,” 25th International Symposium on Power Semiconductor Devices and ICs (ISPSD '13), Kanazawa, Japan, May 26-30, 2013. (Accepted for publication)
  4. A. Shorten and W.T. Ng, “A Segmented Gate Driver IC for the Reduction of IGBT Collector Current Over-Shoot at Turn-on,” 25th International Symposium on Power Semiconductor Devices and ICs (ISPSD '13), Kanazawa, Japan, May 26-30, 2013. (Accepted for publication)
  5. S. Xie and W.T. Ng, “A Low Power All-digital Self-calibrated Temperature Sensor using 65nm FPGAs,” IEEE Int. Sym. on Circuits and Systems (ISCAS 2013), Beijing, China, May 19-23, 2013. (Accepted for publication)
  6. M. Sasaki, H. Nishio, and W.T. Ng, “Dynamic Gate Resistance Control for Current Balancing in Parallel Connected IGBTs,” Applied Power Electronics Conference and Exposition (APEC 2013), Long Beach, CA, pp. 244 - 249, Mar. 17-21, 2013.
  7. S.A. Shen, S. Xie, and W.T. Ng, “A Power and Area Efficient 65 nm CMOS Delay Line ADC for On-chip Voltage Sensing,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 4 pages, Bangkok, Thailand, Dec. 3-5, 2012.
  8. S. Xie and W.T. Ng, “Delay-line based Temperature Sensors for On-chip Thermal Management,” 11th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 4 pages, Xian, China, Oct. 29 2012-Nov. 1 2012.
  9. G. Xie, E. Xu, J. Lee, N. Hashemi, F.Y. Fu, B. Zhang, and W.T. Ng, “Breakdown Voltage Enhancement Technique for RF Process Compatible Power AlGaN/GaN HEMTs,” 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD '12), Bruges, Belgium, pp. 337- 340, June 3-7, 2012.
  10. S. Xie and W.T. Ng, “A 0.02 nJ Self-calibrated 65nm CMOS Delay Line Temperature Sensor,” IEEE Int. Sym. on Circuits and Systems (ISCAS 2012), pp. 3126-3129, Seoul, Korea, 20-23 May 2012.
  11. W.M. Tang, M.T. Greiner, M.G. Helander, Z.H. Lu and W.T. Ng, “Effects of Different Ar/O2 Ratios on the Electrical Properties of CuPc-based TFTs with ZrO2 Gate Dielectric,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tianjin, China, Nov. 17-18, 2011.
  12. S. Xie and W.T. Ng, “A 65nm CMOS Low Power Delay Line Based Temperature Sensor,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tianjin, China, Nov. 17-18, 2011.
  13. G. Xie, E. Xu, J. Lee, N. Hashemi, F.Y. Fu, B. Zhang, and W.T. Ng, “Breakdown Voltage Enhancement for Power AlGaN/GaN HEMTs with Air-bridge Field Plate,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tianjin, China, Nov. 17-18, 2011.
  14. J. Wang, W.T. Ng, A. Prodic, “Flyback Transformer Based Transient Suppression Method for Digitally Controlled Buck Converters,” 2011 IEEE Energy Conversion Congress and Exposition (ECCE 2011), pp. 3354-3361, Phoenix, AZ, Sep. 17-22, 2011.
  15. M.S. Zaman, P.K. Cao, O. Trescases, W.T. Ng, “H2-optimal Thermal Management for Multi-Phase Current Mode Buck Converters,” 2011 IEEE Energy Conversion Congress and Exposition (ECCE 2011), pp. 4177-4182, Phoenix, AZ, Sep. 17-22, 2011.
  16. Y. Zhao, W.T. Ng, “An Energy Conservation Based High-efficiency Dimmable Multi-channel LED Driver,” 2011 IEEE Energy Conversion Congress and Exposition (ECCE 2011), pp. 2576-2580, Phoenix, AZ, Sep. 17-22, 2011.
  17. W.T. Ng, A. Shorten, “Efficiency Enhancement and EMI Suppression via Dynamically Adjustable Gate Driving Strength,” 54th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011), Seoul, Korea, Aug.7-10, 2011.
  18. A. Shorten, A.A. Fomani, W.T. Ng, H. Nishio, and Y. Takahashi, “Reduction of Conducted Electromagnetic Interference in SMPS using Programmable Gate Driving Strength,” 23rd International Symposium on Power Semiconductor Devices and ICs (ISPSD '11), pp. 364-367, San Diego, CA, May 23-26, 2011.
  19. J. Wang, W.T. Ng, and O. Trescases, “Versatile Capabilities of Digitally Controlled Integrated DC-DC Converters,” IEEE Int. Sym. on Circuits and Systems (ISCAS 2011), pp. 293-296, Rio de Janeiro, Brazil, 15-18 May 2011.
  20. P.K. Cao, W.T. Ng, O. Trescases, “Thermal Management for Multi-Phase Current Mode Buck Converters,” Applied Power Electronics Conference and Exposition (APEC 2011), Fort Worth, TX, pp. 1124 - 1129, Mar. 6-10, 2011.
  21. W.M. Tang, M.G. Helander, M.T. Greiner, W.T. Ng, Z.H. Lu, “Electrode effects on the breakdown characteristics of high-k HfO2 metal-insulator-metal capacitors,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Dec. 15-17, 2010.
  22. A. Yoo, J.C.W. Ng, J.K.O. Sin, W.T. Ng, “High performance CMOS-compatible super-junction FINFETs for Sub-100V Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 20.7.1 - 20.7.4, San Francisco, CA, Dec. 6-8, 2010.
  23. X. Gang, B. Zhang, F.Y. Fu, W.T. Ng, “GaN high electron mobility transistors with localized Mg doping and Drain Metal Extension,” 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1341 – 1343, Shanghai, China, Nov. 1- 4, 2010.
  24. A. Akhavan Fomani, A. Shorten and W.T. Ng, “An Integrated Segmented Gate Driver with Adjustable Driving Capability,” 2010 IEEE Energy Conversion Congress and Exposition, pp. 2430 – 2433, Atlanta, Georgia, USA, September 12-16, 2010.
  25. A. Yoo, and W.T. Ng, “Sub-200V Lateral SJ-FINFETs with Low On-Resistance,” International Seminar on Power Semiconductors (ISPS'10), Prague, Czech Republic, Aug. 31 - Sep. 3, 2010.
  26. A. Akhavan Fomani, and W.T. Ng, “A Segmented Gate Driver with Adjustable Driving Capability for Efficiency Optimization,” International Power Electronics Conference (IPEC-2010), pp. 1646 – 1650, Sapporo, Japan, Jun. 21 - 24, 2010.
  27. J. Wang, K. Ng, T. Kawashima, M. Sasaki, H. Nishio, A. Prodić and W.T. Ng, “ A Digitally Controlled Integrated DC-DC Converter with Transient Suppression,” 22nd International Symposium on Power Semiconductor Devices and ICs (ISPSD '10), Hiroshima, Japan, pp. 277 - 280 , June 6-10, 2010.
  28. G. Xie, B. Zhang, and W.T. Ng, “Breakdown Voltage Enhancement for GaN High Electron Mobility Transistors,” 22nd International Symposium on Power Semiconductor Devices and ICs (ISPSD '10), pp. 237 – 240, Hiroshima, Japan, June 6-10, 2010.
  29. Y. Zhao, A. Shorten, H. Nishio, and W.T. Ng, “An Integrated DC-DC Converter with One-Step Digital Dead-time Correction,” 22nd International Symposium on Power Semiconductor Devices and ICs (ISPSD '10), pp. 57 – 60, Hiroshima, Japan, June 6-10, 2010.
  30. Y. Zhao, A. Akhavan Fomani, and W.T. Ng, “One-Step Digital Dead-Time Correction for DC-DC Converters,” Applied Power Electronics Conference and Exposition, APEC 2010, Palm Springs, CA, pp. 132 - 137, Feb. 21 - 25, 2010.
  31. J. Wang, K. Ng, T. Kawashima, M. Sasaki, H. Nishio, A. Prodić and W.T. Ng, “Integrated DC-DC Converter with an Auxiliary Output Stage for Transient Suppression,” 2009 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, Nov. 25-27, 2009.
  32. W.M. Tang, M.G. Helander, M.T. Greiner, G. Dong, W.T. Ng and Z.H. Lu, “Enhanced Performance for OTFT on Glass with HfO2 as Gate Dielectric by UV-Ozone Treatment,” 2009 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, Nov. 25-27, 2009.
  33. Y. Feng, G. Wei, W.T. Ng, and T. Sugimoto, “A 38W Digital Class D Audio Power Amplifier Output Stage with Integrated Protection Circuits,” 21st International Symposium on Power Semiconductor Devices and ICs (ISPSD '09), pp. 53-56, Barcelona, Spain, June 14-17, 2009.
  34. K. Ng, J. Wang, W.T. Ng;, “A digitally controlled transient suppression method for integrated DC-DC converters,” 2008 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Dec. 8-10, 2008.
  35. A. Yoo, M. Chang, O. Trescases, and W.T. Ng, “Smart Power IC Design Methodology Based on a New Figure of Merit (FOM) in Standard CMOS,” 8th International Seminar on Power Semiconductors (ISPS'08), Prague, Czech Republic, 27 -29 August, 2008.
  36. O. Trescases, N. Rahman, A. Prodić, and W.T. Ng, “A 1V Buck Converter IC with Hybrid Current-Mode Control and a Charge-Pump DAC,” IEEE 39th Power Electronics Specialists Conference (PESC 2008), pp. 1122 – 1128, Rhodes, Greece, June 15-19, 2008.
  37. A. Yoo, M. Chang, O. Trescases, and W.T. Ng, “High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in 0.25µm Standard CMOS Process,” 20th International Symposium on Power Semiconductor Devices and ICs (ISPSD '08), pp. 95-98, Orlando, Florida, May 18-22, 2008.
  38. H. Wang, J. Wang, H.P.E. Xu, W.T. Ng, K. Fukumoto, A. Ishikawa, H. Imai, and K. Takasuka, “A 30V EDMOS with Orthogonal Gate Structure Based on a 0.18μm CMOS Technology,” 20th International Symposium on Power Semiconductor Devices and ICs (ISPSD '08), pp. 20-23, Orlando, Florida, May 18-22, 2008.
  39. Y. Onishi, H. Wang, H. P. Edward. Xu, and W.T. Ng, “SJ-FINFET: A New Low Voltage Lateral Superjunction MOSFET,” 20th International Symposium on Power Semiconductor Devices and ICs (ISPSD '08), pp. 111-114, Orlando, Florida, May 18-22, 2008.
  40. H. Wang, A. Yoo, H.P.E. Xu, W.T. Ng, K. Fukumoto, A. Ishikawa, H. Imai, K. Sakai, and K. Takasuka, “A Floating RESURF EDMOS with Enhanced Ruggedness and Safe Operating Area,” 2007 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 279-282, Tainan, Taiwan, ROC, Dec. 19-21, 2007.
  41. A. Yoo, M. Chang, O. Trescases, H. Wang, and W.T. Ng, “FOM (Figure of Merit) Analysis for Low Voltage Power MOSFETs in DC-DC Converter,” 2007 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1039-1042, Tainan, Taiwan, ROC, Dec. 19-21, 2007.
  42. Q. Fung, A. A. Fomani, Y. Feng and W.T. Ng, “Design of a 2-GSample/s Track-and-Hold Amplifier implemented in a 60-GHz SiGe BiCMOS Process,” 2007 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 937-940, Tainan, Taiwan, ROC, Dec. 19-21, 2007.
  43. O. Trescases, A. Parayandeh, A. Prodic and W.T. Ng, “Sensorless Digital Peak Current Controller for Low-Power DC-DC SMPS Based on a Bi-Directional Delay Line,” 38th IEEE Power Electronics Specialist Conference, Orlando, Florida, June 17-21, 2007.
  44. H. Wang, O Trescases., H.P.E. Xu, W.T. Ng, K. Fukumoto, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, K. Sakai, S. Tamura, and K. Takasuka, “A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs,” Proc. IEEE International Symposium on Power Semiconductors and ICs (ISPSD), pp. 181-184, Jeju Korea, May 28-30, 2007.
  45.   O. Trescases, G. Wei, W.T. Ng, H. Nishio, T. Sugimoto, and K. Takasuka, “A Digital Predictive On-Line Energy Optimization Scheme for DC-DC Converters,” Applied Power Electronics Conference and Exposition, APEC’07, Anaheim, CA, pp. 557 - 562, Feb. 25 - Mar. 1, 2007.
  46. H.P.E Xu, O.P. Trescases, I-S.M. Sun, D. Lee, W.T. Ng, K. Fukumoto, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, K. Sakai, S. Tamura, K. Takasuka, and T. Kohno, “Design of a Rugged 60V VDMOS Transistor,” Int. Seminar On Power Semiconductors, ISPS'06, Prague, Czech Republic, Aug. 29 - Sep. 1, 2006.
  47. O. Trescases, G. Wei, W.T. Ng, “A Low-Power DC-DC Converter with Digital Spread Spectrum for Reduced EMI,” 37th IEEE Power Electronics Specialist Conference, Jeju, Korea, June 18-22, 2006.
  48. .   O. Trescases, W.T. Ng, H. Nishio, M. Edo and T. Kawashima, “A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency,” 18th International Symposium on Power Semiconductor Devices and Integrated Circuits (ISPSD '06), pp. 373-376, Naples, Italy, June 4-9, 2006. (Young Researcher Award)
  49.    O. Trescases, Z. Lukic, W.T. Ng, A. Prodic, “Low Power Mixed-Signal Current-Mode DC-DC Converter Using a One-bit Delta Sigma DAC,” Applied Power Electronics Conference and Exposition, APEC '06, Dallas, TX, pp. 700-704, March 19-23, 2006.
  50.    I-S. M. Sun; W.T. Ng; H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka, “A RF lateral BJT on SOI for Realization of RF SOI-BiCMOS Technology,” Silicon Monolithic Integrated Circuits in RF Systems, SiRF2006. Digest pp. 50-53, Jan. 18-20, 2006.
  51.    I.-S. M. Sun, W.T. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, and K. Takasuka. “Novel ultra-low power RF lateral BJT on SOI-CMOS compatible substrate,” 2005 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 317-320, Dec. 19-21, 2005.
  52.    D. Lee, I-S. M. Sun and W.T. Ng, “RF Model of Lateral Bipolar Junction Transistor on Silicon-on-Insulator Substrate,” 2005 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 313-316, Dec. 19-21, 2005.
  53. G. Wei, O. Trescases, W.T. Ng, “A Dynamic Voltage Scaling Controller for Maximum Energy Saving Across Full Range of Load Conditions,” 2005 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 371-374, Dec. 19-21, 2005.
  54. O. Trescases, G. Wei, W.T. Ng, “A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS,” 2005 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 367-370, Dec. 19-21, 2005.
  55.    I.-S. M. Sun, W.T. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, and K. Takasuka, “Novel Ultra-Low Power RF Lateral BJT on CMOS Compatible SOI Substrate,” 2005 IEEE International SOI Conference, Honolulu, Hawaii, pp. 123-125,Oct. 3-6, 2005.
  56. D. Lee, W.T. Ng, “Beamforming System for 3G and 4G Wireless LAN Applications,” 2005 European Conf. on Circuit Theory and Design, Proceedings, pp. III/137 - III/140, vol. 3, Cork Ireland, Aug. 29 - Sep. 2, 2005.
  57. D. Lee, W.T. Ng, “Beam Steering System for 3G and 4G Wireless LAN Applications,” The Second IASTED International Conference On Antennas, Radar, and Wave Propagation, Banff, Canada, pp. 267-271, July 19-21 2005.
  58.    I.-S. M. Sun, W.T. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, Y. Furukawa, H. Imai, A. Ishikawa, S. Tamura, and K. Takasuka, “A Novel SOI Lateral Bipolar Transistor with 30GHz Fmax and 27V BVceo for RF Power Amplifier Application,” 17th International Symposium on Power Semiconductor Devices and ICs, 2005, Proceedings, ISPSD '05, pp. 99-102, May 22-26, 2005. (Young Researcher Award)
  59. V.W.Y. Ma, E.H.P. Xu, W.T. Ng, Y. Hara, Y. Furukawa, K. Sakai, H. Imai, T. Naito, N. Sato, S. Tamura, K. Takasuka, T. Kohno, “Design and Optimization of a 40V, 0.35µm Versatile HV-CMOS Technology,” Int. Seminar On Power Semiconductors, ISPS'04, Prague, Czech Republic, Aug. 31 - Sep. 3, 2004.
  60. X. Wu, M. Couillard, M-S. Lee, J-H. Chen, G.A. Botton, D. Landheer, Z-H. Lu, W-T. Ng, T-S. Chao, “Spatially-resolved EELS and EDS Analysis of HfOxNy Gate Dielectrics Deposited by MOCVD using [(C2H5)2N]4Hf with NO and O2,” Microscopy & Microanalysis 2004, pp. 606-607, Savannah, GA, August 1-5, 2004.
  61. O. Trescases, and W.T. Ng “Variable Output, Soft-Switching DC/DC Converter for VLSI Dynamic Voltage Scaling Power Supply Applications,” IEEE Power Electronics Specialists Conference PESC04, Aachen, Germany, pp. 4149-4155, June 20-25, 2004.
  62. O. Trescases, W.T. Ng, and S. Chen, “Precision Gate Drive Timing in Zero-Voltage-Switching DC/DC converter with Integrated Dead-Time-Locked-Loops,” IEEE Int. Sym. on Power Semiconductor Devices and Integrated Circuits, Tech. Digest, Kitakyushu, Japan, pp. 55-58, May 24-27, 2004.
  63. M. Lee, D. Landheer, X. Wu, M. Couillard, Z.-H Lu, W-T. Ng, and G. Botton, “Nitrogen distribution in HfOxNy gate dielectrics deposited by MOCVD using [(C2H5)2N]4Hf with NO and O2,” 2004 MRS Spring Meeting, San Francisco, April 12-16, 2004.
  64. S. Chen, O. Trescases and W.T. Ng, “Fast Dead-Time Locked Loops for a High-Efficiency Microprocessor-Load ZVS-QSW DC/DC Converter,” EDSSC'03, Tech. Digest, Hong Kong, pp. 391-394, Dec. 16-18, 2003. (Best Circuit Paper)
  65. I-S. M. Sun, H. E. Xu, R. Tam, W.T. Ng, H. Mochizuki, M. Toita, T. Kobayashi, Y. Furukawa, H. Imai, A. Ishikawa, N. Saito, Y. Ueda, Y. Ueshima, S. Tamura, K. Takasuka, T. Kohno, S. Soga, K. Sako, and H. Imai, “Delay Time Constant Analysis for ft Optimization in RF Si/SiGe Bipolar Devices,” EDSSC'03, Tech. Digest, Hong Kong, pp. 323-326, Dec. 16-18, 2003.
  66. V.W.Y. Ma, E.H.P. Xu, W.T. Ng, Y. Hara, Y. Furukawa, K. Sakai, H. Imai, T. Naito, S. Nobuyuki, S. Tamura, K. Takasuka, T. Kohno, “Integration of Complementary EDMOS in a Standard 0.35µm CMOS Technology for 40V Applications,” EDSSC'03, Tech. Digest, Hong Kong, pp. 301-304, Dec. 16-18, 2003.
  67. H.P. Xu, V.W.Y. Ma, I.S.M. Sun, W.T. Ng and Y.C. Liang, “Superjunction LDMOS with Drift Region Charge-Balanced by Distributed Hexagon p-islands,” EDSSC'03, Tech. Digest, Hong Kong, pp. 313-316, Dec. 16-18, 2003.
  68. S. Chen and W.T. Ng, “High-Efficiency Operation of High-Frequency DC/DC Conversion for Next-Generation Microprocessors,” The 29th Annual Conference of the IEEE Industrial Electronics Society IECON '03, Tech. Dig. Vol. 1, Roanoke, VA, pp. 30-35, Nov. 2-6, 2003.
  69. R. Azar, F. Udrea, W.T. Ng, F. Dawson, W. Findlay, P. Waind, G. Amaratunga, “Advanced Electro-thermal SPICE Modelling of Large Power IGBTs,” IEEE Int. Sym. on Power Semiconductor Devices and Integrated Circuits, Tech. Digest, Cambridge, UK , pp. 291-294, Apr. 14-17, 2003.

Other non-refereed publications
  1. W. T. Ng, “Power FINFET, a Novel Superjunction Lateral Power MOSFET,” 2011 CMOS Emerging Technologies Workshop, Whistler, BC, Canada, June 15-17, 2011
    (Invited paper).
  2. W.T. Ng, and A. Yoo, “Advanced Lateral Power MOSFETs for Power Integrated Circuits,” 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2010), pp. 859 - 862 Shanghai, China, Nov. 1-4, 2010.(Invited paper)
  3. W.T. Ng, J. Wang, O. Trescases, and A. Prodić, “Power Management for VLSIs — a Power Electronics Perspective,” The 4th International Symposium on Information Electronics Systems, Sendai Excel Hotel Tokyu 3F, Sendai, Japan, July 7-8, 2010.(Invited paper) http://www.ecei.tohoku.ac.jp/gcoe/
  4. W. T. Ng, J. Wang, Y. Zhao, A. Akhavan Fomani, “Circuit Techniques for High Performance Integrated DC-DC Converters,” 2010 CMOS Emerging Technologies Workshop, Whistler, BC, Canada, May 19-21, 2010.(Invited paper)
  5. W.T. Ng, J. Wang, K. Ng, A. Prodić, T. Kawashima, M. Sasaki, and H. Nishio, “Digitally Controlled Integrated DC-DC Converters with Fast Transient Response,” IEEE Int. Sym. Radio-Frequency Integration Technology (RFIT2009), Singapore, December 9-11, 2009.(Invited paper)
  6. W.T. Ng, M. Chang, A. Yoo, J. Langer, T. Hedquist, H. Schweiss, “High speed CMOS output stage for integrated DC-DC converters,” 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2008), pp. 1909-1912, Beijing, China, Oct. 20-23, 2008.(Invited paper)
  7. W.T. Ng, O. Trescases, and G. Wei, “Output Stages for Integrated DC-DC Converters and Power ICs,” 2007 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 91-94, Tainan, Taiwan, ROC, Dec. 19-21, 2007.(Invited paper)
  8. H. Wang, A. Yoo, H.P.E. Xu, W.T. Ng, K. Fukumoto, A. Ishikawa, H. Imai, K. Sakai, and K. Takasuka, “A Floating RESURF EDMOS with enhanced Safe Operating Area,” International Workshop on The Physics of Semiconductor Devices, Mumbai, India, December 16-20, 2007.(Invited paper)
  9. W.T. Ng, O. Trescases, and G. Wei, “Integrated Power Stages For Switched Mode Power Supplies,” Int. Sym. Power Electronics 2007, Novi Sad, Republic of Serbia, Nov. 7-9, 2007.(Invited paper)
  10. O. Trescases, G. Wei, A. Prodic, W. T. Ng, K. Takasuka, H. Nishio, “Power Management for Portable Audio Applications,” 2007 CMOS Emerging Technologies Workshop, Whistler, BC, Canada, July 11-13, 2007.(Invited paper)
  11. W.T. Ng, O. Trescases, G. Wei, “Integrated Switched Mode Power Supplies Using Digital Controllers,” International Conference on Solid-State and Integrated Circuits Technology, Shanghai, China, October 24-26, 2006.(Invited paper)
  12. W.T. Ng, O. Trescases, “Integrated Digitally Controlled Switched Mode Power Supplies for Portable Applications,” 2006 Emerging Technologies Workshop, Banff, AB, Canada, July 19-21, 2006.(Invited paper)
  13. O. Trescases, and W.T. Ng, “Power Management for Modern VLSI Chips and Leakage Power Reduction Techniques,” International Conference on Solid-State and Integrated Circuits Technology, Beijing, China, pp. 1412-1415, October 18-21, 2004.(Invited paper)
  14. O. Trescases, S. O’Loughlin, and W.T. Ng, “A Smart Motor Controller for E-bike Applications,” IEEE Canadian Review, No. 43, pp. 16-19, Spring 2003.(Invited paper)

Short Courses
  1. W.T. Ng, “Integrated Power Converters – Basic Concepts,” 25th International Symposium on Power Semiconductor Devices and ICs (ISPSD '13), Kanazawa, Japan, May 26-30, 2013. (Invited, Short Course)
  2. W.T. Ng, “Energy Efficient Digital Class D Audio Power Amplifiers,” IEEE Singapore Solid-State Circuits Chapter, Singapore, October 10-11, 2012. (Two Days Short Course)
  3. W.T. Ng, “Smart Power ICs and Devices for Power Management Applications,” IEEE Singapore Solid-State Circuits Chapter, Singapore, November 24-25, 2011. (Two Days Short Course)
  4. W.T. Ng, “Integration of Low Power, High-Frequency Digitally Controlled SMPS—Power Management for Portable Applications,” Institute of Microelectronics (IME) and IEEE Singapore Solid-State Circuits Chapter, Singapore, June 26-27, 2007. (Two Days Short Course)
  5. A. Prodic, W.T. Ng, “IC Implementation of High-Frequency Digitally Controlled SMPS,” Applied Power Electronics Conference and Exposition, APEC’07 Prof. Education Seminars, Anaheim, CA, Feb. 25, 2007.

Archieve Publications



Refereed journal publications (published or accepted)
  1. D. Cho, W.T. Ng, and J.K. Mills, “Multiple Simultaneous Specification (MSS) Control of a High Speed Linear Positioning System Driven by a Brushless DC Motor,” Trans. of ASME J. Dyn. Systems, Meas., and Control, Vol. 123, pp. 296-299, Jun. 2001.
  2. A. Khoueir, Z.H. Lu, W.T. Ng, & Y. Ma, “Ultrathin Oxynitride Formation by Low Energy Ion-Implantation,” Journal Vac. Sci. Tech. A, Vol. 18, Issue 2, pp. 724-729, Mar. 2000.
  3. J. Cai, J.K.O. Sin, P.K.T. Mok, W.T. Ng, and P.T. Lai, “A New Lateral Trench-Gate Conductivity Modulated Power Transistor,” IEEE Trans. Electron Devices, Vol. 46, No. 8, pp. 1788 –1793, Aug. 1999.
  4.    C. Zhu, J.K.O. Sin, and W.T. Ng, “Characteristics of P-channel Polysilicon Conductivity Modulated Thin-Film Transistors,” IEEE Trans. Electron Devices, Vol. 46, No. 7, pp. 1406 –1410, Jul. 1999.
  5.    J. Ranaweera, W.T. Ng, and C.A.T. Salama, “Simulation, fabrication and Characterization of a 3.3V Flash ZEEPROM Array Implemented in a 0.8µm CMOS Process,” Solid-St. Electron., Vol. 43, No. 2, pp. 263-273, Feb. 1999.
  6.    Z. Xu, P.T. Lai, and W.T. Ng, “AC Hot-Carrier-Induced Degradation in NMOSFETs with N2O-based Gate Dielectrics,” IEEE Electron Device Lett. Vol. 18, No. 2, pp. 39-41, Feb. 1997.
  7.    Z. Xu, P.T. Lai, and W.T. Ng, “A Novel Technique of N2O-Treatment on NH3-Nitrided Oxide as Gate Dielectric for nMOS Transistors,” IEEE Trans. Electron Devices, Vol. 43, No. 11, pp. 1907-1913, Nov. 1996.
  8.    J. Ranaweera, I. Kalastirsky, E. Gulersen, W.T. Ng and C.A.T. Salama, “A Novel Programming Method for High Speed, Low Voltage Flash E²PROM Cell,” Solid-St. Electron., Vol. 39, No. 7, pp. 981-989, Jul. 1996.
  9.    Z. Xu, P.T. Lai, and W.T. Ng, “Enhanced Off-State Leakage Currents in N-Channel MOSFET’s with N2O-Grown Gate Dielectric,” IEEE Electron Device Lett. Vol. 16, No. 10, pp. 436-438, Oct. 1995.
  10.    Z. Xu, P.T. Lai, and W.T. Ng, “Mobility Improvement of n-MOSFET’s with Nitrided Gate Oxide by Backsurface Ar+ Bombardment,” IEEE Electron Device Lett., Vol. 16, No. 8, pp. 354-356, Aug. 1995.
  11.    W.T. Ng and C.A.T. Salama, “A CMOS Compatible HVIC Process with Complementary SINFETs,” IEEE Trans. Electron Devices, Vol. 38, No. 8, pp. 1935-1942, Aug. 1991.
  12.    W.T. Ng, S. Liang and C.A.T. Salama, “SINFET Device Modeling,” Solid-St. Electron., Vol. 33, No. 12, pp. 1569-1579, Dec. 1990.
  13. W.T. Ng, S. Liang and C.A.T. Salama, “Schottky Barrier Diode Characteristics under High Level Injection,” Solid-St. Electron., Vol. 33, No. 1, pp. 39-46, Jan. 1990.
  14. W.T. Ng and C.A.T. Salama, “High Speed High-Resolution CMOS Voltage Comparator,” Electron. Lett., Vol. 22, No. 6, pp. 338-339, Jun. 1986.

Refereed conference publications (published or accepted)

  1. W.T. Ng, I-S.M. Sun, H.E. Xu*, H. Mochizuki, M. Toita, T. Kobayashi, H. Imai, A. Ishikawa, N. Saito, Y. Ueda, S. Tamura, K. Takasuka, Y. Furukawa, T. Kohno, S. Soga, K. Sako, H. Imai, Y. Ueshima, “SiGe HBTs for System on Chip Applications,” Int. Sym. New Paradigm VLSI Computing, Tech. Digest, Sendai, Japan, pp. 109-112, Dec. 12-14, 2002.
  2. R. Azar, F. Udrea, W.T. Ng, F. Dawson, P. Waind, B. Findley, M. De Silva, and G. Amaratunga, “Advanced SPICE Modelling of Large Power IGBT Modules,” IAS 2002 Annual Meeting, Vol. 4, Pittsburgh, Pennsylvania, pp. 2433-2436, October 13-18, 2002.
  3. I.S.M. Sun, W.T. Ng, P.K.T. Mok, H. Mochizuki, K. Shinomura, H. Imai, A. Ishikawa, N. Saito, K. Miyashita, S. Tamura, and K. Takasuka, “A CMOS Compatible RF Bipolar Transistor Technology,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced semiconductor Devices (AWAD), Tech. Dig., Cheju-Do, Korea, pp. 301-307, July 5-7, 2001.
  4. E.C.K. Yu, J.K. Mills, and W.T. Ng, “On-Chip Monitoring for Smart Power Integrated Circuits,” ISIC-2001, Tech. Dig., Singapore, pp. 446-449, Sept. 4-5, 2001.
  5. D.H.S. Tam, W.T. Ng, “A Novel Mixed-Mode Adaptive Equalization System for High-Speed 2-Level PAM Signals,” Int’l Sym. on Circuits and Systems (ISCAS-2000), Geneva Switzerland, paper no. IV-749, June, 2000.
  6. A. Khoueir, Z.H. Lu, W.T. Ng, S.P. Tay, & P.T. Lai, “RTP Formed Oxynitride Via Direct Nitridation in N2,” Proc. IEEE Hong Kong Electron Device Meeting, Hong Kong, pp. 104-107, June 24, 2000.
  7. A. Khoueir, Z.H. Lu, W.T. Ng, S. P. Tay, “Growth of ultrathin nitride on Si (100) by rapid thermal N2 treatment,” Electrochemical Society Conference on Rapid Thermal and other Short-time Processing Technology, Toronto, pp. 223-226, May 14-18, 2000.
  8. A. Khoueir, Z.H. Lu, W.T. Ng, P.T. Lai, “Ultrathin Oxynitride Formation by Low Energy Ion-implantation,” International Conference on VLSI and CAD (ICVC), Seoul, Korea, pp. 229 -232, Oct 26-17, 1999.
  9. W.C. Chan, P.K.T. Mok, J.K.O. Sin and W.T. Ng, “Design of Monolithic RF Power Amplifier using Bulk BiCMOS Process,” 42nd Midwest Symposium On Circuits and Systems, Tech. Digest, Vol. 1, Las Cruces, NM, pp. 10-13, Aug. 8-11, 1999.
  10. D. Gradinaru, W.T. Ng, and C.A.T. Salama, “High Voltage High Frequency Silicon Bipolar Transistors,” IEEE Int. Sym. on Power Semiconductor Devices and Integrated Circuits, Tech Digest, Toronto, Canada, pp. 293-296, May 1999. (Best Student Paper)
  11. J. Ranaweera, I. Kalastirsky, A. Dibu-Caiole, W.T. Ng and C.A.T. Salama, “Performance Limitations of a Flash E²PROM Cell, Programmed with Zener Induced Hot Electrons,” NVSM Workshop, Tech. Dig., Monterey CA, February 9-12, 1997.
  12. J. Cai, J.K.O. Sin, V.M.C. Poon, W.T. Ng, and P.T. Lai, “A Fast Switching Insulated-gate p-i-n Diode Controlled Thyristor Structure,” IEEE Int’l Conference on Semiconductor Electronics, Tech. Dig., Malaysia, pp. 122-125, 1996.
  13. Z. Xu, P.T. Lai, and W.T. Ng, “Charge Trapping Properties of N2O-Treated NH3-Nitrided Oxides Under High-Field Stress,” IEEE Region 10 Conference on Microelectronics and VLSI TENCON’95, Tech. Dig., Hong Kong, pp. 256-259, Nov. 6-10, 1995.
  14. J. Cai, J.K.O. Sin, W.T. Ng, and P.T. Lai, “Latch-up Characteristics of a Trench-Gate Conductivity Modulated Power Transistor,” IEEE Region 10 Conference on Microelectronics and VLSI TENCON’95, Tech. Dig., Hong Kong, pp. 424-427, Nov. 6-10, 1995.
  15. Z. Xu, P.T. Lai, and W.T. Ng, “A Novel Techniques of N2O-Treatment on NH3-Nitrided Oxide for Fabricating Gate Oxide in n-MOSFETs,” International Conference on VLSI and CAD, Seoul, Korea, 1995.
  16. Z. Xu, P.T. Lai, and W.T. Ng, “Off-State Gate Leakage Current in N-Channel MOSFET’s with Gate Dielectrics Prepared by Different Techniques,” Proc. IEEE Hong Kong Electron Device Meeting, pp. 19-22, Jul. 1, 1995.
  17. Z. Xu, P.T. Lai, and W.T. Ng, “Electrical Performance and Reliability of n-MOSFET’s with Gate Dielectrics Fabricated by Different Techniques,” Proc. IEEE Hong Kong Electron Device Meeting, Hong Kong, pp. 18-21, Jul. 18, 1994.
  18. O.K. Kwon, T. Efland, S. Malhi, W. Bailey, W.T. Ng, and M. Torreno, “An Optimized RESURF Lateral Triple-Diffused MOS (LTDMOS) Device Module Compatible with Advanced Logic Processes,” IEDM Tech. Dig., pp. 237-240, 1992.
  19. O.K. Kwon, T. Efland, W.T. Ng, S. Malhi, R. Todd and John K. Lee, “Optimized 60-V Lateral DMOS Devices for VLSI Power Applications,” Sym. on VLSI Technology, Tech. Digest, , Oiso, Kanagawa Japan, pp. 115-116, May 28-30, 1991.
  20. W.T. Ng and C.A.T. Salama, “CMOS Compatible Complementary SINFETs,” Proc. Sym. on High Voltage and Smart Power ICs, Los Angeles, pp. 96-103, 1989.
  21. W.T. Ng, C.A.T. Salama and J.K.O. Sin, “P-channel Schottky Injection Field Effect Transistors,” IEDM Tech. Dig., pp. 770-773, 1987.

Other non-refereed publications


  1. D. Prince, H. Xiao, and W.T. Ng, “A 100V, 3 Phase Gate Driver with integrated digital PWM Generation and Current Sampling,” PCIM Europe 2002, Nuremberg, Germany, May 14-16, 2002.
  2. I.S.M. Sun, W.T. Ng, P.K.T. Mok, H. Mochizuki, K. Shinomura, H. Imai, A. Ishikawa, N. Saito, K. Miyashita, S. Tamura, and K. Takasuka, “RF Bipolar Transistors in CMOS Compatible Technologies,” Proc. IEEE Hong Kong Electron Device Meeting, Hong Kong, pp. 108-111, June 30, 2001.(Invited paper).

Patents

  1. Digitally Controlled Integrated DC-DC Converter With Transient Suppression. W.T. Ng, J. Wang, K. Ng, H. Nishio, M. Sasaki, T. Kawashima, Dec. 8, 2011, US Patent US 2011/0298439 A1.
  2. High Speed Orthogonal Gate EDMOS Device and Fabrication. H. Wang, H.P.E. Xu, W.T. Ng, US Patent Application, Sep. 2008.
    This invention involve a unique orthogonal gate structure that can minimize the Miller capacitance (CGD) in lateral power MOSFET, resulting in very high switching speed and low gate drive loss.
  3. Distortion suppression circuit for digital class-D audio amplifier. G. Wei and W.T. Ng, Aug. 17, 2010, Patent US7,777,562 B2.
    This invention provides a unique method of suppressing the harmonic distortion caused by non-ideal switching characteristics of the output stage in class D power amplifier. This work is particular useful for audio amplifiers with a long latency in their digital signal path.
  4. Circuit and method for reducing electromagnetic interference. O. Trescases, W.T. Ng, March 11, 2008, US Patent 7,342,528 B2.
    This is a method to achieve variable frequency operation in a digitally controlled switch mode power supply for the purpose of reducing Electromagnetic Interference (EMI).
  5. Method of fabricating a fast programmable flash E2PROM cell. J. Ranaweera; I. Kalastirsky; E. Gulersen; W.T. Ng; and C.A.T. Salama, March 7, 2000, United States Patent 6,034,896
    This E²PROM relies on zener and/or avalanche breakdown of the modified source and drain to substrate junctions to generate hot electrons for programming. Since the electric field generated is much larger than conventional designs, programming can be significantly faster and at reduced voltage levels.
  6. Windowed source and segmented backgate contact linear geometry source cell for power DMOS processes. Efland; Taylor R. (Richardson, TX); Jones, III; Roy C. (Dallas, TX); Kwon; Oh-Kyong, (Seoul, Republic of Korea); Smayling; Michael C. (Missouri City, TX); Malhi; Satwinder (Garland, TX); Ng; Wai T. (Ontario, Canada), Aug. 12, 1997, United States Patent 5,656,517.
  7. Windowed and segmented linear geometry source cell for power DMOS processes. Efland; Taylor R. (Richardson, TX); Jones, III; Roy C. (Dallas, TX); Kwon; Oh-Kyong, (Seoul, Republic of Korea); Smayling; Michael C. (Missouri City, TX); Malhi; Satwinder (Garland, TX); Ng; Wai T. (Ontario, Canada), Dec. 17, 1996, United States Patent 5,585,657.
  8. Lateral double diffused insulated gate field effect transistor and fabrication process. Oh-Kyong (Plano, TX); Efland; Taylor R. (Richardson, TX); Malhi; Satwinder (Garland, TX); Ng; Wai T. (Thornhill, Canada), Nov. 26, 1996, United States Patent 5,578,514.
  9. Resurf lateral double diffused insulated gate field effect transistor. Kwon; Oh-Kyong (Plano, TX); Efland; Taylor R. (Richardson, TX); Malhi; Satwinder (Garland, TX); Ng; Wai T. (Thornhill, CA), Apr. 11, 1995, United States Patent 5,406,110.
  10. Method of fabricating performance lateral double-diffused MOS transistor. Malhi; Satwinder (Garland, TX); Ng; Wai T. (Plano, TX), Jan. 17, 1995, United States Patent 5,382,535.
  11. Method for forming a self-aligned lateral DMOS transistor. Ng; Wai T. (Thornhill, CA), Kwon; Oh-Kyong (Seoul, Republic of Korea), Nov. 29, 1994, United States Patent 5,369,045.
  12. Lateral double diffused insulated gate field effect transistor fabrication process. Kwon; Oh-Kyong (Plano, TX); Efland; Taylor R. (Richardson, TX); Malhi; Satwinder (Garland, TX); Ng; Wai T. (Thornhill, CA), Apr. 26, 1994, United States Patent 5,306,652.
  13. Performance lateral double-diffused MOS transistor. Malhi; Satwinder (Garland, TX); Ng; Wai T. (Plano, TX), Apr. 19, 1994, United States Patent 5,304,827.

     
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